The present disclosure relates to a Hodge-type phase detector and a clock data recovery circuit making use of the Hogge-type phase detector. In the following description, the technical term “phase detector” is used to imply the same meaning as the technical term “phase comparator.”
FIG. 1 is a block diagram showing a CDR (Clock Data Recovery) circuit 10 provided with a Hogge-type phase detector 11 to serve as a circuit designed for an irregular NRZ (Non-Return-to-Zero) signal (see Hogge, CP etc., “A Self Correcting Clock Recovery Circuit,” Journal of Lightwave Technology, LT 3rd Volume, No. 6, December 1985, p. 1312-1314).
As shown in the figure, the CDR circuit 10 employs the Hogge-type PD (Phase Detector) 11, CPs (Charge Pumps) 12 and 13, a LF (Loop Filter 14) and a VCO (Voltage-Controlled Oscillator) 15.
The Hogge-type phase detector 11 has a first DFF (D-type Flip-Flop) 11a for inputting input data IDT, which is NRZ data, synchronously with an ECCK (Eye Center Clock) signal and outputting a signal Q1.
In addition, the Hogge-type phase detector 11 also has a second DFF 11b for inputting the signal Q1 synchronously with an EECK (Eye Edge Clock) signal having a phase opposite to the phase of the ECCK signal and outputting a signal Q2.
On top of that, the Hogge-type phase detector 11 also has a first EXOR (exclusive logical sum) circuit 11c for detecting logic mismatching of the input data IDT and the signal Q1 output by the first DFF 11a. In addition, the Hogge-type phase detector 11 also has a second EXOR circuit 11d for detecting logical mismatching of the signal Q1 output by the first DFF 11a and the signal Q2 output by the second DFF 11b. 
On top of that, the Hogge-type phase detector 11 also has a buffer 11e for supplying a clock signal CLK output by the VCO 15 to the first DFF 11a as the eye center clock signal ECCK and an inverter 11f for supplying the clock signal CLK output by the VCO 15 to the second DFF 11b as the eye edge clock signal EECK.
A signal output by the first EXOR circuit 11c as an up signal UP drives a charge pump (CP+) 12 for charging electrically a current to the LF 14. On the other hand, a signal output by the second EXOR circuit 11d as a down signal DOWN drives a charge pump (CP−) 13 for discharging electrically a current from the LF 14.
The LF 14 integrates and smoothes currents output and input by the charge pumps 12 and 13 in order to generate a signal input supplied to the VCO 15.
The VCO 15 generates the aforementioned clock signal CLK having a frequency determined by the signal input to the VCO 15. The clock signal CLK is output by the CDR circuit 10 as a recovered clock signal RCCK whereas the signal Q1 generated by the first DFF 11a is output by the CDR circuit 10 as a retimed data signal RTDT.
FIG. 2 shows timing charts of operations carried out by the Hogge-type phase detector 11.
The up signal UP generated by the first EXOR circuit 11c is sustained at a high level during a period between times t1 and t2. The time t1 is a time at which the NRZ data serving as the input data IDT is set up. On the other hand, the time t2 is a time at which the first DFF 11a inputs the input data IDT and outputs the input data IDT as output data Q1 on the rising edge of the eye center clock signal ECCK.
The length of the period of (t2−t1) shows how much the eye center clock signal ECCK is delayed from the setting-up of the input data IDT. That is to say, the length of the period of (t2−t1) is an analog quantity representing a relative phase between the input data IDT and the clock signal CLK generated by the VCO 15.
The down signal DOWN generated by the second EXOR circuit 11d is sustained at a high level during a period between the time t2 and a time t3. As described above, the time t2 is a time at which the output data Q1 is set up by the first DFF 11a. On the other hand, the time t3 is a time at which the second DFF 11b inputs the output data Q1 and outputs the output data Q1 as output data Q2 on the rising edge of the eye edge clock signal EECK.
The pulse width of (t3−t2) of the down signal DOWN is always equal to half the period of the clock signal CLK generated by the VCO 15.
When the CDR loop has settled down in a steady state, on the average, there is established a state of time balance between electrical charging by the up signal UP to the LF 14 and electrical discharging by the down signal DOWN from the LF 14.
Thus, if the absolute value of a current generated by the charge pump (CP+) 12 is equal to the absolute value of a current generated by the charge pump (CP−) 13, the phase of the clock signal CLK generated by the VCO 15 is locked so that the high-pulse width of the up signal UP is equal to the high-pulse width of the down signal DOWN.
Accordingly, the pulse width of the up signal UP is equal to the pulse width of the down signal DOWN and both the pulse widths are equal to half the period of the clock signal CLK generated by the VCO 15. In addition, the rising edge of the eye center clock signal ECCK is locked at the a location separated from the setting-up of the input data IDT by a period equal to half the period of the clock signal CLK generated by the VCO 15. That is to say, the rising edge of the eye center clock signal ECCK is locked in the middle of the NRZ data.